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This book will help engineers write better Verilog/SystemVerilog design and verification code as well as deliver digital designs to market more quickly. It shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages. Each example explains in detail the symptoms of the error, the languages rules that cover the error, and the correct coding style to avoid the error. The book helps digital design and verification engineers to recognize, and avoid, these common coding mistakes. Many of these errors are very subtle, and can potentially cost hours or days of lost engineering time trying to find and debug them.
- Sales Rank: #949051 in Books
- Published on: 2007-06-26
- Original language: English
- Number of items: 1
- Dimensions: 9.30" h x .70" w x 6.20" l, 1.15 pounds
- Binding: Hardcover
- 218 pages
Most helpful customer reviews
4 of 4 people found the following review helpful.
Valuable reference for serious Verilog developers
By Mike K.
Verilog may appear to be "simple" for beginner because it is a loosely-typed language and its syntax is somewhat to that of C. In reality, Verilog is really a complex language and many intricate details and features are buried in the language standard (i.e., LRM, Language Reference Manual). Sometimes these details are counter-intuitive and cause unexpected behaviors (for example, the expressions "(a+b)>>1" and "(0+a+b)>>1" are likely to return different results). This book systematically lists and discusses these gotchas, provides guidelines to avoid these traps, and helps you to develop reliable and robust Verilog codes. It can save you many, many debugging hours down the road. Though somewhat expensive, this book is a valuable reference for serious Verilog developers. A simplified version of this book appears as a conference paper. You can search the web and take a look and decide whether it fits you need.
2 of 2 people found the following review helpful.
At least I'll recognize them
By Melanie D. Typaldos
Just started writing SystemVerilog coming from a background of Verilog and C++ but the Verilog was a bit stale. There are a lot of things about SystemVerilog that seem counterintuitive from C++, such as automatic vs. static variables, that everything is essentially pointers, scoping rules, the way inheritance works. As I started reading the gotchas in this book, I realized I had already made several of them. I still make gotchas that I've read about but at least I recognize them.
0 of 0 people found the following review helpful.
Five Stars
By John F. Hubbard
Really an excellent tour of Verilog pitfalls. Overpriced, but you'll buy it anyway. :)
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